Integrated Circuits, in particular radio frequency (RF) power devices with laterally doped metal oxide semiconductor transistors (LDMOS), up to now use electro static discharge (ESD) protection which comprises an asymmetrical behavior against the gate voltage polarity. The breakdown and turn-on voltages of these ESD devices is about +15V and −0.7V. Therefore, the gate bias setting of an LDMOS product is limited to gate source Voltages Vgs of greater than −0.7V. For high linear efficiency RF-power applications, however, a negative gate voltage swing below −0.7V may occur. In addition, the −0.7V bias voltage may cause some issues with respect to ruggedness under certain RF applications.
Therefore, a need exists to provide a better ESD protection for such integrated circuits.